1. Technical Field
The present invention relates to a semiconductor memory device and a data write and read method thereof, and more particularly, to a semiconductor memory device and a data write and read method thereof, capable of preventing errors from being generated when a data read operation is performed in an asynchronous operation mode after a data write operation has been performed in a synchronous operation mode.
2. Discussion of the Related Art
A Pseudo Static Random Access Memory (PSRAM) is a semiconductor memory device that implements the operation of a Static Random Access Memory (SRAM) by using a memory cell array composed of Dynamic Random Access Memory (DRAM) cells and an SRAM external interface.
Recently, the PSRAM, which uses an asynchronous operation mode as its basic operation mode, has been developed to have a synchronous operation mode. In the synchronous operation mode, control signals and data, such as addresses, commands and so forth, are input or output in synchronization with a clock signal. In the asynchronous operation mode, control signals and data, such as addresses, commands and so forth, are not output in synchronization with a clock signal.
FIG. 1 is a timing diagram for explaining a late write function and a bypass read function in the asynchronous operation mode of the PSRAM.
The late write function means that when a write command is received in response to a write enable signal, an address and data received with the write command are stored in registers while the write command is activated and then written to a corresponding memory cell when a following write command is received. This is different than a normal write function, in which a received address and data are directly written to a corresponding memory cell while a write command is activated.
The bypass read function means that, when a read command is received in response to a write enable signal, if an address received with the read command is equal to an address stored in an address register, data is read from a data register instead of a memory cell.
Referring now to FIG. 1, an address “A” and data “0” are received with a write command WC1 in response to a write enable signal /WE. The write command WC1 is received at a falling edge of the write enable signal /WE. In addition, an address “X” is stored in an address register and data “1” is stored in a data register.
In a late write operation mode, during a first write period (e.g., 1 WRITE PERIOD), the data “1” stored in the data register, instead of the address “A” and data “0” received in response to a first signal S1, is written to a memory cell corresponding to the address “X”.
Next, an address “B” is received with a read command RC1 in response to the write enable signal /WE during a first read period (e.g., 1 READ PERIOD). The read command RC1 is received at a rising edge of the write enable signal /WE. In this case, if data stored in a memory cell corresponding to the address “B” is “0”, data “0” is read out.
The address “A” and data “0” received with the write command WC1 are then respectively stored in an address register and a data register, in response to a second signal S2. Here, the second signal S2 is activated in response to the read command RC1, and is used to control data and an address to be respectively stored in a data register and an address register.
Subsequently, an address “C” and data “1” are received with a write command WC2 in response to the write enable signal /WE during a second write period (e.g., 2 WRITE PERIOD). In the second write period, the data “1” stored in the data register is written to a memory cell corresponding to the address “A” stored in the address register in response to the first signal S1.
Next, the address “C” is received with a read command RC2 in response to the write enable signal /WE during a second read period (e.g., 2 READ PERIOD). At this time, the address “C” and the data “1” received with the write command WC2 are respectively stored in the address register and the data register in response to the second signal S2.
In the second read period, since the address “C” received with the read command RC2 is equal to the address “C” stored in the address register, the bypass read function is performed. In other words, the data “1” stored in the data register, instead of data stored in a memory cell, is output.
However, when the synchronous operation mode is converted into an asynchronous operation mode and a read operation is performed after a data write operation is performed at an address “A” in the synchronous operation mode, if a read address received with a read command is “A”, data stored in a data register, instead of a corresponding memory cell, is output due to the bypass read function.
In this case, if data stored in the memory cell corresponding to the address “A” in the synchronous operation mode is different from data stored in the data register in the asynchronous operation mode, incorrect data will be output. In other words, when the data read operation is performed at the address “A” in the asynchronous operation mode after the data write operation has been performed at the address “A” in the synchronous operation mode, unexpected data may be output, thus causing an error. Accordingly, a need exists for a memory device that is capable of preventing such errors from being generated.